The present invention relates to a cell structure of, for example, a dynamic RAM (DRAM), particularly to a method of forming an element isolation insulating film by means of STI (Shallow Trench Isolation).
In recent years, prominent progress is being achieved in a large scale integration of semiconductor devices, particularly DRAM. In accordance with the progress, the area occupied by the unit memory element in the device tends to be markedly diminished. Also, it is unavoidable for the area occupied by the element isolation region to be diminished. Such being the situation, an STI method has come to be used as an element isolation method in place of the known LOCOS (Local Oxidation of Silicon) method.
A conventional STI method is proposed in, for example, B. Davari et al. "A New Planarization Technique Using a Combination of RIE and Chemical Mechanical Polish (CMP)", IEDM, pp. 61-64, 1989. FIGS. 1, 2A to 2C, 3A to 3C and 4 accompanying the present specification collectively exemplify the conventional STI method proposed in this literature.
Specifically, FIG. 1 is a cross sectional view showing that an insulating film 6 for element isolation is selectively formed in a surface region of a semiconductor substrate 1. On the other hand, FIGS. 2A to 2C and 3A to 3C collectively show the conventional STI method of forming the insulating film 6.
As shown in FIG. 2A, a silicon oxide film 2 and a silicon nitride film 3 are formed in the first step on the surface of the semiconductor substrate 1, followed by forming on the silicon nitride film 3 a resist layer 4 in a predetermined pattern by the known lithography method. In the next step, a reactive ion etching (RIE), which is an anisotropic etching method, is applied to the substrate 1, with the resist layer 4 used as a mask, to form an element isolation region 5 in the semiconductor substrate 1, as shown in FIG. 2B. After formation of the element isolation region 5, a silicon oxide-based insulating film 6 is deposited on the entire surface, as shown in FIG. 2C. Further, a dummy pattern 7 is formed above the large element isolation region in order to moderate the surface irregularity taking place after deposition of the insulating film 6.
In the next step, the entire surface is coated with a resist layer, followed by selectively removing the insulating film 6 and the dummy pattern 7 as well as the coated resist layer by RIE and the known CMP (Chemical Mechanical Polish) method, as shown in FIG. 3A. In this step, the silicon nitride film 3 is used as an etching stopper, with the result that the surface of the substrate is flattened. Then, the silicon nitride film 3 is selectively removed by etching, as shown in FIG. 3B.
Finally, a wet etching using a liquid etchant of HF or NH.sub.4 F is applied to remove the silicon oxide film 2, with the result that an STI is formed in the semiconductor substrate 1, as shown in FIG. 3C. In this wet etching step, the insulating film 6 is over-etched at the boundary region with the element region because the etching proceeds isotropically, as shown in FIG. 3C.
In general, the insulating film 6 buried in a groove consists of silicon dioxide like the silicon oxide film 2. Therefore, in the wet etching step, the insulating film 6 is partly removed together with the oxide film 2, with the result that a concave portion 15 is formed at the edge of the groove.
Further, a gate insulating film 16 and a polycrystalline silicon layer 17 doped with phosphorus are formed in this order to form a laminate structure on the semiconductor substrate 1 having the STI formed thereon, as shown in FIG. 4. As already described, the concave portion 15 is formed in the edge of the groove. It follows that the laminate structure consisting of the polycrystalline silicon layer 17 and the gate insulating film 16 has a thickness B in the concave portion 15 larger than a thickness A in the other portion.
Further, the polycrystalline silicon layer 17 is coated with a resist layer, followed by selectively applying an anisotropic etching such as RIE to the polycrystalline silicon layer 17 coated with the resist layer to form a striped gate electrode. Still further, an impurity is selectively implanted into the semiconductor substrate 1 so as to form diffusion regions (not shown) used as source and drain regions. In the anisotropic etching step, it is difficult to remove completely the thick polycrystalline silicon layer 17 deposited on the gate insulating film 16. In other words, it is unavoidable for some portion of the polycrystalline silicon layer 17 to be left unremoved on the gate insulating film 16. What should be noted is that the residual polycrystalline silicon layer causes a short-circuit problem between adjacent gate electrodes.
In addition, the conventional STI method requires a large number of treating steps, leading to a high cost and a low yield.